The microprocessor industry is developing circuits with shorter and shorter cycle times. Microprocessor designers seeking higher performance are reducing cycle times beyond that which simple process geometry scaling may achieve by using domino logic circuits in a pipeline configuration. The speed of the data path, however, is slowed by the time required to precharge sets of the domino logic circuits in the pipeline.
Domino circuits are used to evaluate a logic operation based on data input to the circuit. The logic operation can be performed within one or more logic stages. Where multiple stages are present, an evaluation of one stage is rippled, or dominoed, through the various stages, with each subsequent stage performing its evaluation based on the previous evaluation. After the completion of the evaluation in the final stage, an output is provided from the domino circuit through an output latch.
Data transfer speed through the domino logic circuits can be increased by electrically precharging a series of logic gates during a first clock phase, and then evaluating the intended logic function during the next clock phase. The critical data path is pipelined in domino logic so that a portion of the domino gates are precharging while another portion of domino gates are evaluating. In traditional domino pipelines, the critical data path is divided into half-cycles where during one half-cycle domino logic gates are precharging and in the other half cycle the domino logic gates are evaluating.
Opportunistic time-borrowing (OTB) domino systems allow for domino pipelines without latches between phase boundaries. In processors, however, the pipeline may need to be stalled due to, for examples, interrupts and data dependencies. In one prior art system, enable latches are inserted between OTB domino phases. When a stall occurs, these latches hold their current value until the stall is released, thereby conserving the current state of the pipeline stage for one to several clock cycles.
FIG. 1A illustrates a prior art domino gate 20 used at the start of a half cycle in a domino pipeline. Domino gate 20 is the first domino gate in a new half cycle. The domino gate 20 consists of an NMOS logic network that performs some predetermined logic function in the pipeline. The logic function is performed using inputs (three shown) received from enable latches 30, 40, and 50 illustrated in FIG. 1B. The enable latch of FIG. 1B requires the enable input (EN) to select between new data at input D and the stored state of data input to the enable latch in a previous cycle. In this manner, the enable latches 30, 40, and 50 hold data from a previous half cycle until the domino gate 20 is ready to process the data.
One problem with such a system is that an additional delay between the previous domino gate and the next phase domino gate is inserted, thereby burdening the critical data path with significant time delay. In addition, the enable signal needs to be strong enough to drive as many latches as inputs that exist in the next phase domino circuit, resulting in a significant design challenge.